1. Field
Embodiments of the inventive concept relate to a nonvolatile memory device and a method of fabricating the same and, more particularly, to a nonvolatile memory device including a memory cell having a transistor in which an insulating isolation layer is formed in a channel region and a method of fabricating the memory device.
2. Description of Related Art
A conventional art disclosed in Korean Patent Publication No. 2001-0056831 relates to a method of forming an anti-fuse of a semiconductor device, more specifically, a method of forming an anti-fuse of a semiconductor device, which may easily break an insulating layer at a lower voltage using a right-angled corner of a semiconductor substrate. The disclosed method includes forming a predetermined pattern on a semiconductor substrate on which a process for a lower structure is completely performed to form a structure having right-angled corners, depositing a gate oxide layer and stacking a nitride layer/a first polysilicon (poly-Si) layer on the gate oxide layer, forming a photoresist pattern to expose the first poly-Si layer formed on the right-angled corners of the semiconductor substrate, dry etching the exposed first poly-Si layer to firstly expose the nitride layer formed on the right-angled corners of the semiconductor substrate, dry etching the nitride layer, and depositing a second poly-Si layer and forming a pattern. In the above-described method of forming the anti-fuse of the semiconductor device, an anti-fuse capable of easily breaking an insulating layer at a lower voltage may be fabricated.
Another conventional art disclosed in Korean Patent Publication No. 1997-0067848 relates to a semiconductor memory device and a method of fabricating the same. The semiconductor memory device includes an access transistor T configured to access information of word lines, a storage node capacitor C configured to store information stored through a bit line due to an operation of the access transistor T, and a charge-up transistor P configured to supply charges to the storage node capacitor C. In the above-described semiconductor memory device, charges may be continuously supplied to the storage node capacitor C so that a processing speed of the semiconductor memory device can be improved.
Meanwhile, a nonvolatile semiconductor memory device may be a semiconductor memory device in which information stored in a memory cell is retained even if power supply is not interrupted.
The nonvolatile memory device may be electrically programmed. A memory device related with the inventive concept may store data by the principle that when a high voltage for a program operation is applied between insulating layers or variable resistors serving as storage layers, resistances of the insulating layers or the variable resistors vary.
The nonvolatile memory device may include memory cells in which storage layers include insulating layers or variable resistors.
When the storage layers include the insulating layers, a high voltage for a program operation may be applied to both electrodes (i.e., a first electrode and a second electrode) between the insulating layers to cause a breakdown. In this case, a resistive path may be generated so that the insulating layers may be changed from an insulation state to a conduction state. Accordingly, the insulating layers may become anti-fuses. When the insulating layers are in the conduction state, the nonvolatile memory device may be in a programmed state, and the programmed state may be defined as storage of data ‘0.’ Also, when the insulating layers are in the insulation state, the nonvolatile memory device may be in an unprogrammed state, and the unprogrammed state may be defined as storage of data ‘1.’
Conversely, the conduction state may be defined as data ‘1,’ and the insulation state may be defined as data ‘0.’
When the storage layers are the variable resistors, the variable resistors may include a resistance variable material or a phase transition material.
In a case in which the variable resistors of the memory cell include the resistance variable material, when a voltage equal to or higher than a set voltage is applied to both electrodes (i.e., a first electrode and a second electrode) between the variable resistors, the variable resistors may be put into a low resistance state, and when a voltage equal to or higher than a rest voltage is applied to the first and second electrodes between the variable resistors, the variable resistors may be put into a high resistance state. Accordingly, the low resistance state may be defined as storage of data ‘0,’ and the high resistance state may be defined as storage of data ‘1.’ Conversely, the low resistance state may be defined as storage of data ‘1,’ and the high resistance state may be defined as storage of data ‘0.’
The resistance variable material is being developed using various materials, such as perovskite, transition metal oxides, and chalcogenides.
Memory devices using the resistance variable material may be classified into several types according to materials. A first type is a memory device in which a colossal magnetoresistance (CMR) material, such as Pr1-xCaxMnO3 (PCMO), is inserted between electrodes and a variation in resistance due to an electric field is used. A second type is a memory device in which a binary oxide, such as niobium oxide (Nb2O5), titanium oxide (TiO2), nickel oxide (NiO), or aluminum oxide (Al2O3), is prepared to have a nonstoichiometric composition and used as a resistance variable material. A third type is a memory device in which a chalcogenide material maintains an amorphous structure and a difference in resistance due to a variation in the threshold voltage of an ovonic switch is used, instead of supplying a large current to the chalcogenide material to change the phase of the chalcogenide material as in a phase-change random access memory (PRAM). A fourth type is a memory device in which a ferroelectric material, such as strontium titanium oxide (SrTiO3) or strontium zirconium oxide (SrZrO3), is doped with chromium (Cr) or Nb to change a resistance state. A final type is a memory device including programmable metallization cells (PMCs) in which silver (Ag) having a high ion mobility is doped into a solid electrolyte, such as germanium selenium (GeSe), so that two resistance states are formed depending on whether or not a conductive channel is formed in a medium due to an electrochemical reaction. In addition, materials or fabrication processes capable of embodying two stable resistance states to obtain memory characteristics have been reported.
In a case in which the variable resistors of the memory cell include the phase transition material, when the phase transition material is in a low resistance state, the low resistance state may be defined as storage of data ‘0,’ and when the phase transition material is in a high resistance state, the high resistance state may be defined as storage of data ‘1.’ Conversely, the low resistance state may be defined as storage of data ‘1,’ and the high resistance state may be defined as storage of data ‘0.’
The phase transition material may be changed into a crystalline phase or an amorphous phase due to a predetermined current. The crystalline phase may correspond to the low resistance state, and the amorphous phase may correspond to the high resistance state.
FIG. 1 is a cross-sectional view of a storage N-channel MOS transistor 990 for explaining a conventional technique related with the inventive concept. Referring to FIG. 1, a typical N-channel MOS transistor 990 may include a thin oxide layer 935, a gate 940 formed of polycrystalline silicon (poly-Si) on the oxide layer 935, sidewall spacers 925 formed on sidewalls of the gate 940, and a source region 926 and a drain region 927 formed apart from each other with the gate 940 therebetween. The source and drain regions 926 and 927 may be doped with an N-type dopant at a high concentration and a low concentration, respectively, and a semiconductor substrate 915 may be doped with a P-type dopant at a low concentration. In the storage N-channel MOS transistor 990, a ground voltage GND having a voltage of about 0 V may be connected to the gate 940, and a program operation may be enabled on the principle that a gate breakdown may be caused in the oxide layer 935 by applying a high voltage to the source region 926 or the drain region 927 to generate a resistive path. Accordingly, an access MOS transistor capable of applying a high voltage for the program operation to the source region 926 or the drain region 927 may be required. A resistive path 936 generated in the oxide layer 935 between the gate 940 and the source region 926 and a resistive path 937 generated in the oxide layer 935 between the gate 940 and the drain region 927, which are paths in which a gate breakdown occurs, are separately illustrated with solid lines for clarity. A thin oxide MOS transistor is used as the storage N-channel MOS transistor 990, while a thick oxide MOS transistor appropriate for high-voltage operations should be used as the access MOS transistor. Also, since the access MOS transistor is needed, there is a fundamental limit to increasing the integration density of memory devices.
FIG. 2 is a circuit diagram of a memory cell 910 including two access N-channel MOS transistors 901 and 902 and one storage N-channel MOS transistor 900, for explaining a conventional technique related with the inventive concept. Referring to FIG. 2, a gate of the storage N-channel MOS transistor 900 may be connected to a ground GND having a voltage of about 0 V. Gates of the access N-channel MOS transistors 901 and 902 may be respectively connected to word lines WL0 and WL1, drains of the access N-channel MOS transistors 901 and 902 may be respectively connected in common to a bit line BL, and sources of the N-channel MOS transistors 901 and 902 may be respectively connected to a source 956 and a drain 957 of the storage N-channel MOS transistor 900.
The above-described configuration of the access N-channel MOS transistors 901 and 902 may be fundamentally limited when it comes to increasing the integration density of memory devices.
To apply a high voltage for a program operation to the source 956 or the drain 957 of the storage N-channel MOS transistor 900 as described above, a high voltage should be transmitted through the access N-channel MOS transistors 901 and 902. Accordingly, a high voltage should be applied to the common bit line BL, and a higher voltage should be applied to the selected word line WL0 to WL1.
According to the conventional techniques, since two oxide MOS transistors having different thicknesses should be formed at a high density in a memory cell, a fabrication process becomes relatively intricate. Also, since three transistors are required to form a memory cell capable of storing 2-bit data, there is a fundamental limit to increasing the integration density of memory devices.